Marketing description

The Pentium II processor delivers outstanding desktop performance today, and provides performance headroom for the advanced applications of tomorrow. It combines the power of the Intel P6 architecture with the capabilities of Intel MMX technology. The latest addition to this processor family is the 450MHz Pentium II processor, which runs with a 100 MHz system bus.
The Intel Pentium II processor is Intel's proven platform for mainstream business desktops, mobile systems, performance-oriented home PCs, and entry-level servers. It combines the advances of the Intel P6 architecture with the instruction set extensions of Intel MMX technology to deliver excellent performance for today's and tomorrow's PC applications.
The Pentium II processor offers exceptional performance for advanced media, communications, and Internet software, including powerful, realistic graphics and imaging capabilities, video conferencing, and the ability to run full-screen, full-motion video. The combination of these advanced technologies make the Pentium II processor a great choice for executing modern compute intensive and multimedia-enhanced application workloads using advanced operating systems. The Pentium II processor also makes an outstanding choice for high performance on mainstream office productivity applications.

Key selling points

• Dynamic Execution technology
• Super pipelining
• Dual Independent Bus (DIB) architecture
• High performance Intel MMX technology
• Write combining

Product features

• Dynamic Execution technology
  Dynamic execution incorporates the concepts of out-of-order and speculative execution. The Pentium II processor's implementation of these concepts removes the constraint of linear instruction sequencing between the traditional fetch and execute phases of instruction execution. Up to 3 instructions can be decoded per clock cycle. These decoded instructions are put into a buffer, which can hold up to 40 instructions.
• Super pipelining
  The pipeline of the P6 processor family consists of approximately 12 stages, versus 5 for the Pentium processor and 6 for the Pentium processor with MMX technology. This enables the Pentium II processor to achieve about a 50% higher frequency than the Pentium processor on the same manufacturing technology. The sophisticated, two-level, adaptive training, and branch prediction mechanism of the Pentium II processor is key to maintaining the efficiency of the super pipelined micro architecture.
• Dual Independent Bus (DIB) architecture
  This architecture consists of two distinct buses emanating from the Pentium II processor: the L2 cache bus and the system bus (used for memory and I/O requests). The L2 cache bus speed scales with processor frequency. Unlike the Pentium processor's system bus, the Pentium II processor's system bus supports up to 8 outstanding bus requests (4 per processor). This allows more parallelism between processors and I/O, as well as supporting smooth performance scaling to a 2 processor system. The GTL+ electrical signaling of the system bus facilitates the migration of this bus to higher frequencies as higher performance DRAM technologies come to market.
• High performance Intel MMX technology
  Intel's MMX media enhancement technology is a major extension of the Intel Architecture that makes PCs into richer multimedia and communications platforms. This technology introduces 57 instructions oriented to highly parallel operations with multimedia and communications data types. These instructions use a technique known as SIMD (Single Instruction, Multiple Data) to deliver better performance for multimedia and communications computation.
• Write combining
  The Write Combining technology of the P6 architecture can be used to achieve very high graphics I/O performance. This feature combines multiple writes to a region of memory (for example, a video controller's frame buffer) declared as WC type into a single-burst write operation. This is well suited for the bus, which is optimized for burst transfers. The combining also leads to burst writes of cache line sizes. These writes are further combined by the chipset, leading to high throughput for graphics I/O.